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(ELEC4410)[2012](s)midterm~wpwong^_44206.pdf
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HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Department of Electronic and Computer Engineering
ELEC 4410 - CMOS VLSI Design
Spring 2012

March 23, 2012 Midterm Exam Duration: 150 minutes

STUDENT NUMBER: FAMILY NAME: FIRST NAME:
Q1
Q2
Q3
Q4
Q5
Total


TURN OFF YOUR PHONE
Write your student number, family name, and first name (no acronyms).
Copy sheets and books are NOT permitted.
No electronic equipment. No calculator.


Q1: (25pt) Determine whether the following statements are true or false. No explanation is necessary. Read the sentences carefully.
(1)
(1pt) In an n-type doped silicon the majority carriers are electrons. TRUE

(2)
(1pt) Transistors in an integrated circuit are fabricated sequentially, one transistor at a time. FALSE

(3)
(1pt) The input impedance of a CMOS circuit is low. FALSE

(4)
(1pt) High input impedance is a critical requirement for a transistor technology to be suitable for VLSI. TRUE

(5)
(1pt) Circuit designers adjust the strength of a MOSFET typically by tuning the channel width. TRUE

(6)
(1pt) Sizing of a MOSFET is quantized by the manufacturing grid. TRUE

(7)
(1pt) In a PMOS transistor, the surface is strongly inverted when the density of mobile holes in the channel becomes equal to the density of holes deeper in the bulk. FALSE

(8)
(1pt) The saturation current increases quadratic with VGS in a MOSFET with constant VDS. TRUE

(9)
(1pt) The saturation current displays a weak dependence on the drain-to-source voltage (VDS) due to the modulation of the channel length. TRUE

(10)
(1pt) Enhanced carrier mobility is one of the goals of CMOS technology scaling for achieving faster circuits. TRUE

(11)
(1pt) Increasing the source voltage of a PMOS transistor (while maintaining the body voltage constant) decreases the threshold voltage. FALSE

(12)
(1pt) A reverse body biased NMOS transistor produces less current due to lower threshold voltage. FALSE

(13)
(1pt) The diameter of a wafer is limited by the fabrication cost that is primarily determined by the defect density and yield of a CMOS fabrication process. TRUE

(14)
(1pt) A larger wafer yields more dies, thereby reducing cost of an integrated circuit and increasing the profit margin of a semiconductor company. TRUE

(15)
(1pt) Photolithography is the technique of selective etching/deposition of layers of materials using light to form an integrated circuit. TRUE

(16)
(1pt) Scaling the gate oxide thickness enhances the field effect, thereby increasing the current produced by a MOSFET. TRUE

(17)
(1pt) Gate oxide thickness is a parameter that can be tuned on a layout by a circuit designer. FALSE

(18)
(1pt) A 22nm CMOS technology means a technology with a gate-oxide thickness of 22nm. FALSE

(19)
(1pt) MOSFET is a 4 terminal device. TRUE

(20)
(1pt) Well and substrate contacts should be avoided since th