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(ELEC303)2007_mid_elec303_by_PPSpider.pdf
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2007 ELEC 303 Midterm Examination (5 questions and 8 pages)
0. Write down your NAME: Solutions and STUDENT NUMBER:
Answer only on two sides of the question papers.
1. Design and Implementation by SPLD and FPGA (15%)
a) The following digital clock finite-state machine (FSM) takes 1MHz clock input and display hours, minutes and seconds readings on 6 7-segment displays. Describe how many Spartan CLBs are required for this digital clock FSM?
Hours Minutes Seconds

It requires a long counter to divide the 1MHz clock to 1Hz. If we use 6 decade (10) counters and each counter requires 4FFs or 2 CLBs, then it needs 12 CLBs The 60 counter for seconds requires 8 outputs or 4 CLBs.
The 60 counter for minutes requires 8 outputs, or 4 CLBs The 24 counter for hours requires 8 (or 6) outputs, or 4 (or 3) CLBs The carry outputs to next stages are available form XQ or YQ, no extra CLB is required.
6 BCD-to-7-segment display decoders require 6 x7=42 outputs, or 21 CLBs
In total, it requires12 + 4 + 4 + 4 + 21 = 45 CLBs.
2. MAPPING, PLACEMENT AND ROUTING (15%)
A state machine has the following state equations
Q1+ = SQ1 + Q2

Q2+ = Q1 + TQ2 = TQ2 + Q1
Z = STQ1 + TQ2 = TQ2 + STQ1 Where Q1 and Q2 are state registers; S and T are inputs; and Z is output. Q1 has been placed and mapped into a logic block below.
Complete the implementation of this state machine by writing 0 or 1 into the SRAM cells. (Hint: Firstly re-express each function in truth table and write output values into the look up tables, then complete routing between logic blocks.)
There are many possible designs. Here is one example.
Both Q2+ and Z have the same function with that of Q1+, so their SRAM cells would have the same
values with that of Q1+. STQ1 is a AND gate. The example placement is routing is below
Q1 Q2 S Q1+ Z
0 0 0 0T
0 0 1 0 S
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1



SPARTAN AND SPARTAN-II (25%)
a) XC2S15-TQ144-6 used in the laboratory does not have enough capacity, so a XC2S50-TQ144-6 is used to implement a logic design. How many 4-input look-up tables and input/output blocks are available in this XC2S50-TQ144-6 device? How many SRAM cells are in this device? (6%)
b) The Spartan-II device has a delayed lock loop (DLL) to generate and synchronize clocks. For an input clock of 120MHz, how many different clocks that this DLL can generate? (3%)
c) Both the Spartan and Spartan-II devices have switch matrices that connect wire segments from one direction to the other three directions. How many single-length lines that a Spartan switch matrix can connect to? How many single-length lines that a Spartan-II switch matrix can connect to? Name three routing resources that are available in Spartan-II, but not available in Spartan device. (6%)
d) Estimate how many Spartan CLBs are required in order to implement an 8-bit x 8-bit multiplier? Is it possible to implement a 16-bit x 16-bit multiplier in XC2S15? Please expla