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(ELEC301)[2011](s)midterm~716^_37714.pdf
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HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Department of Electronic and Computer Engineering
ELEC 301 - CMOS VLSI Design
Spring 2011

March 25, 2011 Midterm Exam Duration: 120 minutes

STUDENT NUMBER: FAMILY NAME: FIRST NAME:
Q1
Q2
Q3
Q4
Q5
Total

TURN OFF YOUR PHONE
Write your student number, family name, and first name (no acronyms).
Copy sheets and books are NOT permitted.
No electronic equipments other than a simple calculator.


Q1: (25pt) Determine whether the following statements are true or false. No explanation is necessary. Read the sentences carefully.
(1)
(1pt) In an n-type doped silicon the majority carriers are electrons. TRUE

(2)
(1pt) In a MOSFET the current conduction primarily occurs deep in the body of the device through a thick layer of carriers. FALSE

(3)
(1pt) Transistors in an integrated circuits are fabricated sequentially, one transistor at a time. FALSE

(4)
(1pt) The input impedance of a CMOS circuit is low. FALSE

(5)
(1pt) High input impedance is a critical requirement for a transistor technology to be suitable for VLSI. TRUE

(6)
(1pt) Circuit designers adjust the strength of a MOSFET typically by tuning the channel width. TRUE

(7)
(1pt) Sizing of a CMOS integrated circuit is quantized by the manufacturing grid. TRUE

(8)
(1pt) In a PMOS transistor, the surface is strongly inverted when the density of mobile holes in the channel becomes equal to the density of holes deeper in the bulk. FALSE

(9)
(1pt) The saturation current increases quadratic with VGS in a MOSFET with constant VDS. TRUE

(10)
(1pt) The saturation current displays a weak dependence on the drain-to-source voltage (VDS) due to the modulation of the channel length. TRUE

(11)
(1pt) Enhanced carrier mobility is one of the goals of CMOS technology scaling for achieving faster transistors. TRUE

(12)
(1pt) The threshold voltage of a PMOS transistor is negative. TRUE

(13)
(1pt) Increasing the source voltage of a PMOS transistor decreases the threshold voltage. FALSE

(14)
(1pt) A reverse body biased NMOS transistor produces less current due to lower threshold voltage. FALSE

(15)
(1pt) The diameter of a wafer is limited by the fabrication cost primarily determined by the defect density and yield of a CMOS fabrication process. TRUE

(16)
(1pt) Due to the self-aligned fabrication process, the polysilicon gate has the same type of doping with the source and drain areas of a MOSFET. TRUE

(17)
(1pt) Scaling the gate oxide thickness enhances the field effect, thereby increasing the speed of transistors. TRUE

(18)
(1pt) Gate oxide thickness is a parameter that can be tuned on layout by the circuit designer. FALSE

(19)
(1pt) A 45nm CMOS technology means a technology with a minimum diffusion width of 45nm. FALSE

(20)
(1pt) MOSFET is a 2 terminal device. FALSE

(21)
(1pt) Well and substrate con