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(ELEC301)[2010](s)final~2123^_10317.pdf
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Spring 2010
ELEC 301 - CMOS VLSI Design
Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology

May 20, 2010 Final Exam
STUDENT NUMBER:
SURNAME:
FIRST NAME:


TURN OFF YOUR PHONE
Write your student number, surname, and first name (no acronyms).
SOLUTION

You cannot leave within the first 30 and the last 15 minutes of the exam.

Consider the given circuit with the following input vector transitions:
Transition 1: ABCDE = 11111 -> 00011 B is known to arrive (1 -> 0 transition) earlier as compared to C. And C is known to arrive (1 -> 0 transition) earlier as compared to A.
Transition 2: ABCDE = 00000 -> 00110 D is known to arrive (0 -> 1 transition) earlier as compared to C.
Would you recommend pin reassignments to enhance the output transition speeds (for both input vector transitions) as compared to the original pin assignments shown in the layout?
If your answer is yes, draw the modified circuit schematic with the new pin assignments. Explain.
If your answer is no, explain why the current pin assignments (as shown in the layout) are optimum for achieving the maximum output transition speed with these input arrival times.
Yes, a pin reassignment is recommended to enhance the output transition speed for both input vector transitions.
For the pull-up: The earlier arriving signals should be applied to the transistors closer to the power
supply.
With the following pin assignments, C3 will be charged to VDD when B arrives.

After some delay C will arrive. C2 will be charged to VDD.
When finally A arrives, the pullup path needs to charge only CL since C2 and C3 are already fully charged to VDD. Output low-to-high transition would therefore be faster with the pin assignments shown in the following figure.
2pt
For the pull-down: The earlier arriving signal (D) should be applied to the transistor closer to the
ground. C1 is fully discharged after D arrives. When finally C arrives, the pulldown path needs to discharge only CL since C1 is already discharged.
2pt
VDD

Q2 (14pt) Consider the following circuit with two outputs. Fill in the following truth table with the steady-state output voltages (8pt). Determine the output functions of this circuit (out1 and out2). Write the Boolean functions of the outputs in terms of the inputs (6pt). Power supply voltage = 2V.
A

B
B

A B Out1 Out2
0V 0V 0V 2V
0V 2V 2V 0V
2V 0V 2V 0V
2V 2V 0V 2V

Each correct entry in the Table: Out1 = A XOR B
1pt
3pt
Out2 = A XNOR B
3pt
Q3 (24pt) Consider the following circuits driving identical loads.
Input


Output
Circuit 1:





Cin
CL



CL

The maximum input capacitance (Cin) is equivalent to the maximum gate-oxide capacitance of a 30 wide and 2 channel length (W = 30 and L = 2) MOSFET. The load capacitance (CL) is 1000 times the input capacitance.
(a) (10pt) Determine the minimum delay achievab