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(ELEC301)[2009](s)mid~ee_cswab^_10316.pdf
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HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Department of Electronic and Computer Engineering
ELEC 301 - CMOS VLSI Design
Spring 2009

March 31, 2009 Midterm Exam Duration: 100 minutes


TURN OFF YOUR PHONE
Write your first name and family name (no acronyms).
Copy sheets and books are NOT permitted.
No electronic equipments other than a simple calculator.
Attempt all of the questions.

Write clearly. You can write to the back of the papers. Do not hesitate to ask for additional blank papers if you need.
Q1: (20pt) Determine whether the following statements are true or false. No explanation is necessary. Read the sentences carefully.
(1)
(1pt) With constant VDS, the saturation current increases almost linearly with VGS in a short-channel MOSFET primarily due to the aggressive scaling of the supply voltage with each new technology generation. FALSE

(2)
(1pt) The saturation current displays a weak dependence on the drain-to-source voltage (VDS) due to the modulation of the channel length with VDS. TRUE

(3)
(1pt) Carrier mobility decreases with the enhanced electric field between the source and drain terminals of a MOSFET. TRUE

(4)
(1pt) Carrier velocity decreases with the enhanced electric field between the source and drain terminals of a MOSFET. FALSE

(5)
(1pt) Long-channel transistor model overestimates the maximum current produced by a short-channel MOSFET. TRUE

(6)
(1pt) PMOS transistors experience more severe velocity saturation as compared to NMOS transistors. FALSE

(7)
(1pt) The PMOS to NMOS transistor width ratio (required for similar output low-to-high and high-to-low propagation delays) is increased with technology scaling in a CMOS inverter. FALSE

(8)
(1pt) Total gate-oxide capacitance of a saturated MOSFET is reduced as compared to a cut-off transistor. TRUE

(9)
(1pt) Longer channel length transistors are employed in the I/O circuitry to avoid punch-through when exposed to unusually high voltages. TRUE

(10)
(1pt) Battery lifetime could be extended in portable applications if the integrated circuits could be cooled below the room temperature, since the subthreshold leakage current is reduced at a lower temperature. TRUE

(11)
(1pt) The threshold voltage of a PMOS transistor is negative. TRUE

(12)
(1pt) Increasing the drain voltage of a PMOS transistor lowers the threshold voltage. TRUE

(13)
(1pt) As the channel length of an NMOS transistor is increased, the threshold voltage increases. TRUE

(14)
(1pt) A reverse body biased NMOS transistor produces less current with a lower threshold voltage. FALSE

(15)
(1pt) Scaling the supply voltage enhances the maximum gain in the transition region of a CMOS inverter (assuming sufficiently high supply voltage for strong inversion, VDD > |Vt0|). TRUE

(16)
(1pt) Due to the self-aligned fabrication process, the polysilicon gate has the same type of doping with the sour