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(ELEC151)2008_s_midterm2_elec151.pdf
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08-1 Flip-flops (20%)
In the following is a master/slave D flip-flop made of 4 inverters and 4
transmission gates.


a) Replace one inverter by a 2-input NOR gate and another inverter by a 2-input NAND gate, and add one more inverter, so a Positive Asynchronous Set can be applied to this D flip-flop. This Positive Asynchronous Set can set Q to 1 immediately and hold the value till the next clocking event. (10%)
b) Add a Positive Synchronous Set to this D flip-flop with extra logic gates. The Positive Synchronous Set can set Q to 1 at the clocking event when CLK=1. (5%)
c) Write a VHDL code for b) (5%)
08-2 Reverse Engineering (20%) Find all the state transitions and draw a state transition diagram for the following counter. Express the states in (ABC) where A is for the most significant bit (MSB).

08-3 Counter Designs (20%)
Use J-K flip-flop as the first flip-flop, D flip-flop as the second flip-flop and T flip-flop as the third flip-flop to design a three-bit Gray code counter that counts in the following sequence: 000, 001, 011, 010, 110, 111, 101, 100, 000, and repeat. Just write down the Boolean expressions for the flip-flop inputs. Do not have to draw the schematics.
Present state Next State Remapped Next State A B C A+B+C+ JAKADB TC 000 001 0x0 1 001 011 0x1 0 010 110 1x1 0 011 010 0x1 1 100 000 x10 0 101 100 x00 1 110 111 x01 1 111 101 x00 0

08-4 Laboratory and TTL IC Counters (30%)
You are given TTL IC counters 74LS90, 74LS92 and 74LS93 as below,

Please use these counters and extra logic gates to design a digital clock that takes 1Hz clock input and display hours (12H) and minutes readings on the 7-segment displays through the BCD-to-7-segment decoder 74LS47 as below,

a) Draw the circuit diagram of this digital clock counter with TTL IC counters (25%) (Note that this circuit has one input and 16 outputs)
b) How many TTL IC counters are required (5%)
08-5 VHDL Design of a Counter (15%) Write a VHDL code to design a presettable BCD up/down counter, 74LS190, as shown on the next page by behavioral architecture. (Use UD, CE, CP, Q(0), Q(1), Q(2), Q(3), TC, P(0), P(1), P(2), P(3) and PL for the input/output signals) 08-6 VHDL Design of a 4-bit adder (10% bonus question) In the lecture note, we have shown a VHDL design of a 4-bit adder by a top structural architecture of cascaded full adder and a bottom dataflow architecture of the full adder. We have mentioned in the class that this 4-bit adder can be designed by just a dataflow architecture. Please try this design.