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(ELEC151)2008_s_fianl_elec151.pdf
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2008 ELEC151 ---Final Examination
(6 Questions and 3 Pages, Open Note of One A4 Sheet, Two Sides) (Answer only on two sides of the answer booklet)

08-1 Design Process C A Sequence Detector (20%)

Design a sequence detector which investigates an input sequence X and produces
an output Z = 1 when the 4-bit-in-a-group input sequence of "0110" or 1010 has
been seen.
a) Show the minimized state-transition diagram for the Moore machine (5%)
b) Show the minimized state-transition diagram for the Mealy machine (5%)
c) Use the binary assignment and D flip-flops to implement the Mealy machine

and show the next-logic (10%).

08-2 Logic Optimization and VHDL Synthesis (15%)
The state transition table of a sequential circuit is shown below.
a) Simplify this state transition table. (5%)
b) Use one-hot assignment and write a VHDL code to synthesize this circuit.

(10%)
Present Next State Output
State X=0 X=1 X=0 X=1
A DH 01
B FC 11
C DF 01
D CE 01
E CD 11
F DD 11
G DC 11
H BA 11


08-3 Common Knowledge of Digital Designs and Systems (15%
a) The four major types of integrated circuits are microprocessor, memory, logic and analog. What was the total revenue of the integrated circuits in 2007? Which type contributed the most?
b) What was the total revenue of the PLD in 2007? Who was the largest supplier of PLD? c) We used GAL20V8 SPLD in the laboratory. Who produced this GAL20V8? What is the typical cost of this GAL20V8? d) Who is the largest integrated circuit company in Hong Kong? What was it revenue in 2007? e) What are three key components in a digital system?
ELEC151 Final Exam. 16-Dec-2008, 1/3


08-4 VHDL Synthesis ---A Digital Clock (25%)

In the mid-term exam, we have used TTL IC counters to design a digital clock that takes 1Hz clock input and display hours (12H) and minutes readings on the 7-segment displays through the BCD-to-7-segment decoder 74LS47 as below. In the final exam, we will use SPLD for the Digital Clock Counter. Please write the VHDL code.

ENTITY clk_counter IS
PORT (CP: IN STD_LOGIC;

Q: OUT STD_LOGIC_VECTOR (15 downto 0)); END clk_counter;

08-5 Reverse Engineering-Synchronous Logic (15%)
Draw the complete state transition diagram for the following finite-state machine. The states are represented by (QA QB QC).

QA

X
QA
X

QA
QC


QC

QA
X
QC


ELEC151 Final Exam. 16-Dec-2008, 2/3

08-6 SPLD (10%)
ESTIMATE the typical gate count of a logic that the P22V10 PAL can implement. How many programming elements are in this
P22V10? In the following is the logic diagram of the P22V10.


ELEC151 Final Exam. 16-Dec-2008, 1/3