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(ELEC151)2007_s_midterm1_elec151.pdf
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07-1. 2007 Elec151 Midterm Exam #1, p2/8 Boolean Expressions and K-map (15%) Given a Boolean function F(A,B,C,D) = m(8,12,13) + d(1, 2, 3, 6, 7, 11) a). Simplify this Boolean function in sum of minterms. (5%) b). Simplify this Boolean function in product of maxterms. (5%) c). In CMOS technology, what is the minimum number of transistors required to implement this function in two-level design. (5%) 07-2. 2007 Elec151 Midterm Exam #1, p3/8 Two-level Combinational Logic (20%) Design a TWO-BIT MULTIPLIER to calculate R = P x Q, where P = A 2 + B and Q = C2 + D are the 2-bit input numbers, and R = W 8 + X 4 + Y2 + Z is the 4-bit output number. Do the design according to the following instructions. a). Construct the truth table. (5%) (Inputs are A, B, C and D. Outputs are W, X, Y and Z) b). Express the output bit X and Y in K-map. (5%) c). Write down the minimized Boolean expressions for X and Y in sum-of-products form. (5%) d). Draw the circuit schematics with AND, OR and NOT gates for X and Y according to the Boolean expressions in c). (5%)

(This page is intentionally left blank for answer or practice) 07-3. Design with TTL ICs (20%)
Design and draw a 3-bit by 2-bit binary multiplier that multiplies A (A2A1A0) and B
(B1B0) for C (C4C3C2C1C0) with ONLY 2-input AND gates from 74LS08 and 2-
input XOR gates from 74LS86. How many TTL ICs are required for this multiplier?
2007 Elec151 Midterm Exam #1, p4/8 2007 Elec151 Midterm Exam #1, p5/8


07-6. Multi-level Logic, Waveform and Glitch (10%) We have shown in the lectures that the following half adder had a glitch in SUM when the inputs were changed from A=0 and B=1 to A=1 and B=0. Please try to design a new half adder that has no glitch in the outputs. (It is a simple circuit and can be done in 5 minutes if you do it right.)

2007 Elec151 Midterm Exam #1, p8/8