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(ELEC151)2007_s_fianl_elec151.pdf
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2007 ELEC151 ---Final Examination
(6 Questions and 3 Pages, Open Note of One A4 Sheet, Two Sides) (Answer only on two sides of the answer booklet)
07-1 Design Process C A Sequence Detector (15%)

Design a sequence detector which investigates an input sequence X and produces an output Z = 1 WHENEVER the input sequence of "010" or 110 has been seen. a) Show the state-transition diagrams for the Moore machine (5%) b) Use the row-matching method to get and draw the most simplified state-
transition diagram. (5%)
c) Use the binary assignment and D flip-flops (DA and DB, express AB as the states) to implement the Moore machine and show the next-logic in minimized 2-level Boolean expressions (5%).

07-2 Logic Optimization and VHDL Synthesis (15%)
The state transition table of a sequential circuit is listed below.
a) Find the minimized state transition table using the Implication Chart. (5%)
b) Use Gray-code assignment and write a VHDL code to synthesize the

minimized transition table obtained in a). (10%)
Present Next State Output Z
State X=0 X=1 X=0 X=1

A CE 00
B HG 01
C BA 00
D AB 10
E EC 10
F HD 01
G AF 10
H BF 01
I FA 00

07-3 Laboratory Design Implementations (20%) Design a digital clock finite-state machine (FSM) to take 1Hz clock input and display the readings of hours and minutes on 4 7-segment displays. The 1Hz clock has a period of 1 second. Divide the 1 Hz clock by a 60 counter can get a clock of 1 minute period. Further divide this 1 minute clock by a 10 and a 6 counter can get a clock of 1 hour period and also the reading of minutes in 2 BCD numbers. These 2 BCD numbers can go through 2 BCD-to-7-segment decoders to drive and show the minutes readings on 2 7-segment displays as below. Continue with the similar approach for the readings of hours (24H), and add an output function, Ring, which will be high for 2 minutes when the clock is 11:10 (time to hand in the exam papers).
ELEC151 Final Exam. 14-Dec-2007, 1/3


a) Estimate how many TTL ICs are required for this digital clock FSM? (5%) Describe how many of these TTL ICs are MSI? (5%) (You have learned all the required TTL ICs in your laboratories to design this circuit. Do not have to write down the IC number if you cannot remember, but have to specify what kinds of ICs are used.)
b) Describe how many macrocells are required for this digital clock FSM? How many CPLD are required to implement this finite-state machine, and what is the cost? (10%)
07-4 VHDL Synthesis ---A BCD Up/Down Counter (20%) We have studied a BCD up/down counter in the textbook, and the equivalent TTL IC 74LS190 in the lecture note. In this question, please design this presettable BCD up/down counter as shown below by VHDL. (It is much simpler to do with the behavorial architecture; it is almost impossible to design with structural architecture)


Note:


ELEC151 Final Exam. 14-Dec-2007, 2/3

ENTITY bcd_counter IS
PORT (CP, UD, CEB, PLB: IN STD_L