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(ELEC151)2006_s_fianl_elec151.pdf
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2006 ELEC151 ---Final Examination
(6 Questions and 3 Pages, Open Note of One A4 Sheet, Two Sides) (Answer only on two sides of the answer booklet)
0 Name and Student Number
Write down your name and student number on the answer booklet.

06-1 Design Process C A Sequence Detector (20%)
Design a sequence detector which investigates an input sequence X and produces an output Z = 1 WHENEVER the input sequence of "0101" or 0110 has been seen. a) Show the minimized state-transition diagrams for both the Moore and Mealy
machines (10%)
b) Use one-hot assignment and write a VHDL code to synthesize this sequence detector in Moore machine. Write only the ENTITY and ARCHITECTURE blocks (10%)

06-2 Logic Optimization and VHDL Synthesis (20%)
The state transition table of a sequential circuit is list below.
a) Simplify this state transition table. (10%)
b) Use binary assignment and write a VHDL code to synthesize this circuit.

(10%)
Present Next State Output Z
State X=0 X=1 X=0 X=1
A CE 00
B HG 01
C BA 00
D AB 10
E EC 10
F HD 01
G AF 10
H BF 01


06-3 Design Process C A Vending Machine (15%)
A vending machine delivers a package of gum after 20 cents are deposited. The machine has single coin slot for nickels (5 cents) and dimes (10 cents). The machine can make change when it delivers the gum. In other words, the vending machine has two outputs. One is for gum delivery (GUM) and the other is for a nickel change (CHANGE). a) Show both the minimized state-transition diagrams for both the Moore and
Mealy machines (10%), Use [Gum, Change] for the output in the states. b) Use binary assignment and D flip-flops to implement this Vending machine in Mealy machine. Find the minimized output logic functions. (5%)
ELEC151 Final Exam. 12-Dec-2005, 1/3

06-4 Laboratory Design Implementations (20%) Design a digital clock finite-state machine (FSM) to take 1Hz clock input and display hours and minutes readings on 4 7-segment displays. The 1Hz clock has a period of 1 second. Divide the 1 Hz clock by a 60 counter can get a clock of 1 minute period. Further divide this 1 minute clock by a 10 and a 6 counter can get a clock of 1 hour period and also the reading of minutes in 2 BCD numbers. These 2 BCD numbers can go through the corresponding BCD-to-7-segment decoders to drive and show the minutes readings on 2 7-segment displays as below. Continue with the similar approach for the hours (24H) readings

a) Describe how many TTL ICs are required for this digital clock FSM? (10%) (You have learned all the required TTL ICs in your laboratories to design this circuit. Do not have to write down the IC number if you cannot remember, but have to specify what kinds of ICs are used.)
b) Describe how many GAL22V10 are required for this digital clock FSM? (10%)
06-5 Reverse Engineering-Synchronous Logic (15%) Draw the complete state transition diagram for the following finite-state machine. The states are represented by