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(ELEC151)2005_s_midterm2_elec151.pdf
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06-1. Latches and Flip-flops (15%) a) Design and draw a negative level-sensitive D latch using two transmission gates and necessary inverters. (5%) b) Design and draw a negative edge-triggered J-K flip-flop using a positive edge-triggered T flip-flop and necessary primitive gates. (5%) c) Design and draw a low level-sensitive D flip-flop using a low level-sensitive J-K flip-flop and necessary primitive gates. (5%) (Note the edge-triggered and level-sensitive flip-flops have different symbols)
06-2 4-bit Serial Adder-Subtractor (15%) In the textbook and lecture note, we have shown a serial adder made of two shift registers, one full adder and one D flip-flop. The shift register A is used to store both the augend and the sum, and the shift register B takes a serial input (SI). Add a control input M and necessary logic gates to make this serial adder a serial adder-subtractor that performs addition A+B when M=0, and subtraction A-B when M=1. Assume A B all the time for the subtraction. This serial adder-subtractor also requires a clear input (CLR) to reset the D flip-flop before the addition, and a preset input (PR) to preset the D flip-flop before the subtraction. The logic diagrams of the 4-bit shift register, full adder and D flip-flop are shown below.

a) Draw the circuit diagram of this 4-bit serial adder-subtractor, which has SI, CLK, M, PR and CLR inputs. (10%)
b) Explain how many clocks are required to perform 4-bit subtraction P-R assuming that both the shift registers are initially empty or 0000 and PR. (5%)
Counter Designs (15%) Use J-K flip-flop as the first flip-flop (MSB, most significant bit), D flip-flop as the second flip-flop and T flip-flop as the third flip-flop (LSB, least significant bit) to design a three-bit Gray code counter that counts in the following sequence: 000, 001, 011, 010, 110, 111, 101, 100, 000, and repeat. Just write down the Boolean expressions for flip-flop inputs. Do not have to draw the schematics.
VHDL Designs C Combinational Logic (15%) Write a VHDL code to design quadruple 2-to-1 multiplexers with enable as shown below. Use data-flow architecture for this design. (Write only the ENTITY and ARCHITECTURE blocks)

VHDL Design C Sequential Logic (20%) Write a VHDL code to design a 4-bit up-down binary counter as shown below by structural architecture (Write two VHDL codes for TFF and 2-to-1 multiplexer as Components, and a third VHDL code to call these two components for the counter. Note that the 2-to-1 multiplexer has 4 inputs and 3 outputs, and the TFF has two inputs and two outputs.)

06-6 555 Timer (20%) We used 555 timer as a clock generator in Lab 4 to generate clocks for the sequential circuit. The circuit diagram and formula of this 555 timer are shown below. a) Use a 555 timer to generate a 10 KHz clock of 80% duty cycle. Use 0.1uF capacitance for C1. Determine the values of Ra and Rb. (5%) b) Use a 555 timer and necessary logic gates to generate a 10 KHz clock of 20% duty