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(ELEC151)2004_s_midterm2_elec151.pdf
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05-1. D Latch (15%) a). Use only 4 NOR gates and necessary inverters to design a negative level-sensitive D latch. (5%) b). Use only 2 transmission gates and necessary inverters to design a positive level-sensitive D latch. (5%)
c). Use only 1 transmission gate, 1 tri-state inverter and necessary inverters to design a positive level-sensitive D latch. (5%) (Hint: use the tri-state inverter to replace one transmission gate and one inverter in (b).)
The positive and negative level-sensitive D latches can be represented by the following symbols, respectively.

05-2 Shift Register (20%) The logic diagram of an electronic lamp handball is shown below. The ball is simulated by a moving light that is shifted left or right through the bidirectional shift registers. The functional table the 74194 shift register is available on the next page.
(a)
The circuit is first initialized with the Reset switch. What happens to the Shift registers after the player presses the Reset switch? (4%)

(b)
During the game, what is the position of the Reseat switch? Open or close? (2%) (Note that the input is treated as logic 1 if it is open in TTL IC.)

(c)
After the circuit is initiated, what happens if the player presses the Start switch? (2%)

(d)
During the game, what is the position of the Start switch? Open or close? (2%)

(e)
After the Reset and Start switches are pressed, the player must press the Pulser button. What happens to the shift registers when the Pulser button is pressed? (2%)

(f)
What frequency of the CLK should we use in this circuit? (2%) (there is no standard answer, just give your best guess)

(g)
After the Pulser switch is pressed, what is the pattern of the indicator lamps after 5 clocks? (2%) (Use 8 bits, for example, 01010011 or 00010010 to indicate the values of the lamps)

(h)
After the Pulser switch is pressed, what is the pattern of the indicator lamps after 10 clocks? (2%)

(i)
How many clocks later after the Pulser switch is pressed, the user has to press the Pulser switch again to bounce the ball back? (2%)



05-3 Counter Designs (15%) Use J-K flip-flop as the first flip-flop (MSB, most significant bit), D flip-flop as the second flip-flop and T flip-flop as the third flip-flop (LSB, least significant bit) to design a three-bit counter ABC (A=MSB) that counts in the following sequence: 110, 101, 100, 011, 010, 001, 000 and repeat. Just write down the Boolean expressions for flip-flop inputs. Do not have to draw the schematics.
05-4. VHDL Designs C combinational logic (15%) Write a VHDL code to design a full adder on the right with data-flow architecture (Write only the ENTITY and ARCHITECTURE blocks)

05-5 VHDL Design C Sequential Logic (20%) Write a VHDL code to design a 4-bit storage register with rising edge trigger and active-low asynchronous reset as below by a) structural architecture (10%) (The VHDL code of the DFF is available below, just write the top-