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(ELEC101)tutorial02.pdf
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Tutorial 02 --
DC Circuits

Fall 2006
ELEC101 BASIC ELECTRONICS


Outline

.Basic Definitions

CBranch

CNode

CLoop

CMesh

.Circuit Theorems

CEquivalence

CSeries and Parallel

CKCL

CKVL

CVoltage Divider

CCurrent Divider




I-V Relation of R, L and C

Related Equation
Energy Equation

Resistor R

Inductor L

Capacitor C








Basic Definitions

Circuit diagram is a graphical representation of a circuit (closed connection of circuit elements). An example of circuit diagram:



Branch

Each two terminal elementcorresponds to one
branchof the circuit diagram.



Node

Node is the junction where the terminals of two or more circuit elements are electrically interconnected.

Node



Loop

Loop is a closed paththrough the circuit with no node is crossed more than once, and the beginning node is also the end node



Mesh

Mesh is a loop that does not contain other loop.
It is the simplest loop.



Equivalence

Two resistive one-port networks are said to be equivalent if they have the same v-icharacteristic (curve) across the two terminals for ALL LOADor SOURCE.

Network
A

Network
B

If I1 = I2 and V1= V2 then network A network B
A resistive one port can be replaced by any equivalent resistiveone port without changing the behavior of the rest of the circuit.

Text Box: V1


Text Box: V2



Series Connection

Two terminal elements connected "end-to end" are said to be connected in series (elements have same current).

Note: Resistors in series connection
1.The current through each resistor is the same.

2.Individual potential difference is proportional to the individual resistance.

3.The total equivalent resistance is greater than any individual resistance.





Parallel Connection

Two terminal elements connected "side-by-side" are said to be connected in parallel (elements have same voltage).

Note: Resistors in parallel connection
1.The potential difference across each resistor is the same.

2.The total equivalent resistance is smallerthan the smallestindividual

resistance





Kirchhoffs Current Law (KCL)

Total current flowing into (or leaving) the a node must be zero OR
Total current flowing into the node = Total current leaving the node
i.e. The algebraic sum of the currents at any node is zero.



Kirchhoffs Voltage Law (KVL)

In any closed loop of a circuit, the algebraic sum of the voltage is zero OR
Voltage drop across the loop = Voltage apply across the loop.


Text Box: Applying KVL on the circuit, we getVs C V1 C V2 C V3 = 0 OR Vs = V1 + V2 + V3

Voltage Divider




Current Divider



Real Voltage Source

When r = 0, Vab= Vs




Real Current Source

When r = , I = Is