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(COMP381)quiz2_solutions_comp381_by_PPSpider.pdf
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COMP 381 Quiz #2

Name: __________ Student No.: __________ Lecture Section: ___
There are 5 questions on 11 pages in this quiz. Please check and report any missing pages.


Q1. [16 Points] Multiple choices
a) _A__ With a VLIW design, which of the following components can be simplified?
A. Processor
B. Physical memory (DRAM)
C. Cache
D. Compiler
b) _B__Which one of the following types of hazards can be reduced by register renaming?
A. RAW hazards
B. WAR hazards
C. Control hazards
D. Structural hazards
E. All of the above
c) _D__ Which one of the following items does NOT directly affect a processors ability to exploit ILP? Assume that the computer system has only one single-core processor, only one single-threaded program runs on the system, and the physical memory is large enough to hold all the active pages thus no virtual memory swapping is needed.
A. The design of the branch predictor
B. The number of registers
C. The number of instructions a processor can issue every cycle

D. The mapping (correspondence) between virtual page numbers and

physical page numbers
E. The optimization level used for compiling the programs
d) _C__ A computer engineer wants to use loop unrolling to make a program run faster on a target computer. He finds that the program has many loops but all loops in the program iterate exactly four times. Also, there are no nested loops (there are no loops inside another loop). So he decides to unroll every loop in the program four times. With such a loop unrolling, which of the following components actually will be likely to perform LESS efficiently? Assume all these components exist on the target computer.
A. The processors pipeline
B. Register file
C. Cache
D. None of the above

Q2. [16 Points] True, false, and why?
Determine whether the following statements are true or false, and briefly explain your point.
a) There are no compulsory misses with a cache of infinite size.
False. Since the first access to a block will cause a compulsory cache miss so that this block can be brought into the cache.
b) Two programs with an identical instruction mix (using the same types of instructions and having the same number of instructions for each type) running on the same computer must have the same cache miss rate.
False, different orders of instructions also affect the happen of cache miss.
c) Over the last 20 years, the performance of the processor and the DRAM improves at the same rate in terms of throughput and latency.
False, processor improved faster in the past 20 years.
d) A loop which contains 20 instructions and iterates for 10000 times has no temporal or spatial locality if none of the 20 instructions are memory access instructions (e.g., load/store instructions).
False. Execution of the program requires fetching instructions from memory to the (instruction) cache. Instruction fetching usually shows a strong temporal or spatial locality.